In the current semiconductor industry, electronic packaging has become an important direction of the industry development. The development of packaging technology for decades has made the high-density and small-size packaging requirements become the main stream direction of encapsulation.
Wafer-level Fan-out package, by reconstructing a wafer and wafer-level rewiring way, fills the package surface with I/Os through a rewiring plane array, in order to expand I/O pitches and satisfy pitch demands of the next level interconnection. At present, the material for reconstructing the wafer is mainly molding compound, or an organic material such as a semi-cured wafer used for the substrate package, so as to realize the plastic sealing of the fan-out structure of the functional chip, and finally cut into a single package.
At present, through the research and development and industry promotion for many years, the wafer-level fan-out package is considered to be an advanced packaging technology with a large number of I/Os and good integration flexibility. With the development of smart phones, 3D stacking technology requirements are proposed for the fan-out type package. For example, Package on Package (PoP) was used to encapsulate integrated a microprocessor chip and memory chip, and the lower package of PoP uses BGA packaging mode. Now, forming the micro-processed 3D fan-out type packaging structure by making vertical through holes in the molding compound, which can replace the PoP lower packaging mode, and can achieve a higher density and a smaller size interconnection. Moreover, from the perspective of the industrial chain, it can be directly completed in a foundry or packaging factory without substrate materials.
With the development of electronic products towards to thinner, lighter, higher pin density, lower cost, and system integration, the single functional chip packing technology has gradually cannot meet industrial demands, and the emergence of the fan-out wafer-level packaging technology provides an opportunity for the packaging industry to develop towards the low cost packaging. Thus, the fan-out wafer-level technology is currently developing into the next generation major packaging technology.
However, the outstanding problem of the current fan-out type package is that the molding compound is used to reconstruct the wafer, and there is a great difference between the processing of the molding compound wafer and the manufacture of the traditional silicon wafer. Photolithography, development, exposure, fabrication of fine metal lines and planting balls on silicon wafers are very mature. However, the molding compound itself is very unsuitable for the above processes, especially for the foundry. Therefore, in order to develop a fan-out process based on molding compound wafers, many process challenges need to be overcome, and customized relevant equipment is needed to solve the difficult problems including holding of the easy-to-warp molding compound wafer and the preparation of fine lines on the surface of the molding compound. Furthermore, from the perspective of the structure itself, the difference of thermal expansion coefficients between the molding compound and silicon is large, which will bring reliability problems. It has been reported that the fan-out structure is not suitable for the ultra-high 12×12 mm2 package. For chips with high power consumption, the heat dissipation of the molding compound is also a problem.